Generally, in system circuits of semiconductor devices, a clock signal has been used as a reference signal for adjusting operation timing or guaranteeing high-speed operation without an error. When a clock signal from an external circuit is used in an internal circuit, a time delay (or clock skew) is generated and then a DLL has been used to compensate such a time delay by providing the same phase between the external and internal clock signals. As compared with the phase locked loop (PLL), the DLL has an advantage in that it is less sensitive to a noise than the PLL. Adoringly, the DLL has been widely used in synchronous memories such as DDR SDRAMs (Double Data Rate Synchronous DRAMs) and also a register controlled DLL has been generally used as a DLL circuit.
Referring to FIG. 1, a conventional register controlled DLL includes first and second clock buffers 11 and 12, a clock divider 13, a phase comparator 19, a delay unit 10, which has first to third delay lines 14 to 16, a delay monitor 23 having a shift register 17 and a shift controller 18 in a DLL loop, first and second DLL drivers 20 and 21 and a delay model 22. The first clock buffer 11 receives an inverted external clock signal /clk and produces a first clock signal fall_clk synchronized with a falling edge of the clock signal /clk. Likewise, the second clock buffer 12 receives the external clock signal clk and produces a second clock signal rise_clk synchronized with a rising edge of the clock signal clk. The clock divider 13 divides the second clock signal rise_clk into n (n: a positive integer, typically n=8) signals and then produces a reference signal ref and a delay monitoring signal dly_in. The first delay line 14 receives the first clock signal fall_clk according to an amount of delay from the shift register 17, which is controlled by the shift controller 18, and produces a first internal clock signal ifclk. Also, the second delay line 15 receives the second clock signal rise_clk according to an amount of delay from the shift register 17, which is also controlled by the shift controller 18, and produces a second internal clock signal irclk. The first and second DLL drivers 20 and 21 receive the first and second internal clock signals ifclk and irclk and produce first and second DLL clock signals fclk_dll and rclk_dll, respectively. The third delay line 16 receives the delay monitoring signal dly_in from the clock divider 13 and produces a delayed clock signal feedback_dly. The delay model 22 receiving the delayed clock signal feedback_dly provides the same signal processing path to the delayed clock signal feedback_dly as the actual signal processing path. The phase comparator 19 compares the output from the delay model 22 with the reference signal ref and provides a control signal ctrl to the shift controller 18 according to a phase difference. The shift controller 18 outputs a shift right or left signal SR or SL to the a shift register 17 in response to the control signal ctrl and the first to third delay lines 14 to 16 shift the input clock signals (i.e., fall_clk and rise_clk) based on an amount of shift stored in the shift register 17. Also, the shift controller 18 outputs a DLL locking signal dll_lockb when there is no phase difference between the output from the delay model 22 and the reference signal ref. The delay model 22 includes a dummy clock buffer, a dummy output buffer and a dummy load, which is called a replica circuit. The shift register 17 and the shift controller 18 forms a delay control signal generator 23 to control the first to third delay lines 14 to 16 within a delay unit 10.
The DLL operation in FIG. 1 will be described in detail below. The first clock buffer 11 receiving the external clock signal clk from the external circuit produces the first clock signal fall_clk and the second clock buffer 12 receiving the inverted external clock /clk produces the second clock signal rise_clk. The clock divider 13 produces n clock signals in response to the second clock signal rise_clk, thereby forming the reference clock signal and the delay monitoring signal dly_in which are synchronized with the external clock signal clk every n divided clock signals.
At initial operation, the delay monitoring signal dly_in passes through the third delay line 16 in the delay monitor 10, thereby forming the delayed clock signal feedback_dly, and the delayed clock signal feedback_dly is delayed in the delay model 22 for forming another delayed clock signal (another feedback signal).
The phase comparator 19 compares the rising edge of the reference signal ref with that of the feedback signal and then produces the control signal ctrl. The shift controller 18 produces shift control signals SR and SL, each of which determines the right or left shift in the shift register 17, in response to the control signal ctrl from the phase comparator 19. Also, the shift register 17 determines an amount of the right or left shift of the first to third delay lines in the delay unit 10 in response to the shift control signals SR and SL. Comparing the delayed feedback signal feedback with the reference signal ref on the DLL feedback loop, a delay locking is achieved at the time a minimum jitter is made between them and the delay locking signal dll_lockb is produces as a signal notifying such a locking.
Once the phase locking is achieved, the DLL clock is continuously toggled, except for refresh and power-down modes. Accordingly, this continuous toggling of the DLL clock increases power consumption and, especially, this power consumption is much more at high frequency operation.
As mentioned above, since the conventional register controlled DLL has a time difference between the reference signal ref and the delay monitoring signal dly_in in proportion to a period of the external clock (tCK), a large number of unit delay elements in the delay line are require to compensate such a delay in order that these two signals are in phase. Accordingly, the increase of the unit delay elements causes a wider area of the architecture in the DLL and it takes a longer time to achieve the phase locking. Also, the longer time for phase locking inevitably consumes a large amount of current.
Furthermore, the delay locked loop has to accompany a little jitter. However, in the case where an amount of delay in each unit delay element is not small, the jitter which is caused by the difference between the reference signal ref and the feedback signal may have a large amount.